Citation :

Mummareddy Ramya Krishna, B. Ramana Kumar, 2023. "Design and Analysis of RADIX-8 Based 32-Bit Pipelined Multiplier" ESP International Journal of Advancements in Computational Technology (ESP-IJACT)  Volume 1, Issue 2: 11-19.

Abstract :

In microprocessors, microcontrollers, and signal processing applications, arithmetic operations are essential. Digital Signal Processing (DSP) modules such as Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), and others frequently employ the multiplication operation. The main issue in multiplier design is to reduce power dissipation while enhancing performance. Different logic combinations are utilized in power reduction strategies like Recoding (RADIX-8 Modified Booth Encoding (MBE) structure) to generate Partial Product Rows (PPRs), which are employed in modified pipelined multipliers. For addition between produced PPRs, two addition algorithms are used: sequential based CLA and tree based carry Look-a-head Adder (CLA). When comparing the performance of the RADIX-8 pipelined multiplier with the above-mentioned methodologies to the RADIX-4 pipelined multiplier that is currently in use, the updated method produces a significant, somewhat crucial path latency, area, and power consumption reduction. FPGA technology is used in XILINX 14.7 to implement modified design.FC320-5 XC3S500E.

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Keywords :

Pipelined Multiplier, RADIX-8 MBE, Partial Products Generation, Sequential and Tree Based CLA Addition.