Citation :

C V P Supradeepthi, B Veena, M Hima Bindu, 2023. "Design of Delay Efficient Multiplier Using Parallel Prefix Adders" ESP International Journal of Communication Engineering & Electronics Technology (ESP- IJCEET)  Volume 1, Issue 2 : 1-5

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Abstract :

As technology advances, the demand for speedy and efficient real-time digital signal processing applications has grown. Every application requires multiplication as one of the main arithmetic operations. To boost their speed, a vast number of multiplier designs have been devised. A new technique for designing High-Speed multipliers is proposed in this work. With four 8X8 approximate multipliers, three parallel prefix adders [PPA], and one OR gate, this proposed 16X16 approximate multiplier construction is offered. The insertion delay of the parallel prefix adder is longer, resulting in a faster increase in the superior for the count. The 8X8 multiplier was built using the approximation tree compressor [ATC] and the carry maskable adder [CMA]. In comparison to the traditional Wallace Tree Multiplier, the proposed multiplier has a shorter delay. In the Xilinx ISE 14.7 design suite, all multiplier structures are created in Verilog. In terms of area (number of LUTs) and delay, the proposed designs are compared to typical multiplier designs (ns).

References :

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Keywords :

Approximate Multiplier, Parallel prefix Adders, Brentkung Adder, Han Carlson Adder, Ladner Fishcer Adder, Kogge Stone Adder.