Elvi Bronje-da-Gocha, Gridouane DD, 2026. "Thermo-Electrical Coupled Modeling in High-Density VLSI Interconnects under Nano scale Effects" ESP International Journal of Emerging Multidisciplinary Research [ESP-IJEMR] Volume 2, Issue 1: 64-79.
The relentless trend of semiconductor technologies scaling into the deep nanometer regime has significantly changed the performance, reliability and design methodologies for VLSI systems. Traditionally, reduced transistor sizes have been the driving force behind performance improvements; however, as modern integrated circuits approach the limits of scaling, interconnects are becoming one of the main bottlenecks. In high-density VLSI systems, the interconnects cannot be treated as ideal conductors anymore as they show complicated electrical, thermal and physical-chemical interactions which need to be accurately modelled for preserving system integrity.
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Architecture,Thermo-electrical coupling, VLSI interconnects, Nano scale effects, Joule heating, electro migration, thermal gradients, R C delay.