Citation :

Lakshmi Durga Nujiveeti, R Vinay Kumar, 2023. "A Low Power 6T SRAM using Sleep Power Reduction Technique" ESP International Journal of Communication Engineering & Electronics Technology (ESP- IJCEET)  Volume 1, Issue 2 : 20-24

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Abstract :

     One type of memory component is static random access memory (SRAM). SRAM is in high demand in SOCs due to its unique data-retention capabilities. For the sake of anticipating future needs, this memory part became the subject of study. The importance of power leakage in chip design has grown as SRAM densities have increased. Recent years have seen significant progress in SRAM's ability to reduce power consumption. Mary methods have been developed to provide both dynamic and static power reduction. Today's memory technology is primarily concerned with improving speed and reducing power consumption. In light of this, the research focuses on a low power SRAM that employs a hybrid sleep transistor approach and compares it to traditional SRAM in terms of delay: power dissipation and power delay product(PDP). Using this method, the delay and power requirements of SRAM are decreased. All parameters and stimulations are based on the TANNER MENTORGRAPHICS 250nm technology.

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Keywords :

     SRAM, System on chip (Soc), MTCMOS, Scaling.