Citation :

S. Jasmine, D. Ajitha, 2023. "Area Efficient Nano Approximate an using QCA Designer" ESP International Journal of Communication Engineering & Electronics Technology (ESP- IJCEET)  Volume 1, Issue 3 : 23-33

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Abstract :

        This study delves into the realm of approximate computing, where computational errors and imprecisions are embraced as acceptable trade-offs to achieve more efficient and resource-conserving solutions. The research focuses on the design of approximate adders within the framework of Quantum-dot Cellular Automata (QCA), a promising technology for ultra-low-power computation. Approximate adders are circuits that introduce controlled errors into addition operations to reduce resource consumption while maintaining adequate precision. Two distinct approaches are explored in this study: the utilization of threshold gates and the adaptation of Arithmetic Logic Units (ALUs) to create QCA-based approximate adders. These approaches aim to strike a balance between precision and computational resources, ultimately offering more energy-efficient solutions. Additionally, novel majority inversion-based approximate adder architecture is proposed, emphasizing significant area reduction. The study's findings shed light on the potential of approximate computing in QCA-based systems, paving the way for simplified, energy-efficient, and error-tolerant computational solutions.

References :

[1] A. T. Vanaraj, M. Raj and L. Gopalakrishnan, "Energy-Efficient Coplanar Adder and Subtractor in QCA," 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT), 2020, pp. 539-544, doi: 10.1109/ICSSIT48917.2020.9214274.
[2] P. U. Rao and P. Niranjan, "Design of efficient BCD adder with five input majority generators for quantum cellular automata," 2020 3rd International Conference on Intelligent Sustainable Systems (ICISS), 2020, pp. 1566-1573, doi: 10.1109/ICISS49785.2020.9316010.
[3] Z. Chu, Z. Li, Y. Xia, L. Wang and W. Liu, "BCD Adder Designs Based on Three-Input XOR and Majority Gates," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1942-1946, June 2021, doi: 10.1109/TCSII.2020.3047393.
[4] U. B. Joy, S. Chakraborty, S. Tasnim, M. S. Hossain, A. H. Siddique and M. Hasan, "Design of an Area Efficient Quantum Dot Cellular Automata Based Full Adder Cell Having Low Latency," 2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST), 2021, pp. 689-693, doi: 10.1109/ICREST51555.2021.9331135.
[5] K. Swetha, K. L. Krishna, J. V. S. Sowmya, D. S. Reddy, G. Pravallika and G. A. Kumar, "Area Efficient Multilayer Arithmetic Logic Unit Implementation in Quantum-dot Cellular Automata," 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV), 2021, pp. 584-589, doi: 10.1109/ICICV50876.2021.9388584.
[6] S. Perri, F. Spagnolo, F. Frustaci and P. Corsonello, "Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 11, pp. 3456-3460, Nov. 2021, doi: 10.1109/TCSII.2021.3077669.
[7] K. Kalpana, B. Paulchamy, S. Chinnapparaj, K. Mahendrakan and A. AbdulHayum, "A Novel design of Nano scale TIEO based single layer full adder and full subractor in QCA paradigm," 2021 5th International Conference on Intelligent Computing and Control Systems (ICICCS), 2021, pp. 575-582, doi: 10.1109/ICICCS51141.2021.9432098.
[8] S. Prasanna A, B. Madhava Reddy and R. S R, "Design of Combinational Arithmetic Circuits using Quantum Dot Cellular Automata," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 117-122, doi: 10.1109/ICOEI51242.2021.9453069.
[9] D. Tripathi and S. Wairya, "An Energy Dissipation and Cost Optimization of QCA Ripple Carry Adder," 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021, pp. 760-765, doi: 10.1109/SPIN52536.2021.9566068.
[10] S. Sharma and V. K. Sharma, "Design of Full Adder and Parity Generator Based on Reversible Logic," 2021 Emerging Trends in Industry 4.0 (ETI 4.0), 2021, pp. 1-4, doi: 10.1109/ETI4.051663.2021.9619268.
[11] B. Aravinth and L. J. A. Marcilin, "Implementation of coplanar approximate adders in QCA," 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016, pp. 680-684, doi: 10.1109/WiSPNET.2016.7566219.
[12] T. Zhang, W. Liu, E. McLarnon, M. O'Neill and F. Lombardi, "Design of Majority Logic (ML) Based Approximate Full Adders," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8350962.
[13] A. N. Bahar and K. A. Wahid, "Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 12, pp. 2530-2539, Dec. 2020, doi: 10.1109/TVLSI.2020.3013724.
[14] S. Perri, F. Spagnolo, F. Frustaci and P. Corsonello, "Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 11, pp. 3456-3460, Nov. 2021, doi: 10.1109/TCSII.2021.3077669.
[15] A. Sanchez-Macian, A. Martin-Toledano, J. A. Bravo-Montes, F. Garcia-Herrero and J. A. Maestro, "Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2021.3136204.

Keywords :

        Digital Circuits, Locking Technique, Computing, Quantum-Dot.